With the rapid increase in the volume of data consumption on mobile devices, the need for high bandwidth, compact, and low power receiver circuitry is growing. To support the high data volumes, SERDES (Serializer-Deserializer) circuits must satisfy stringent performance specifications, such as low bit error rates (BERs). Low BERs require CDRs (clock and data recovery circuits) with low jitter components. The rapidly growing throughput speeds for various I/O (input/output) standards is causing CDR design specifications to become more demanding and complicated.
Clock and data recovery is a critical task in serial communication systems. CDR circuits are used in a wide range of applications including transceivers, chip-to-chip interconnects and backplane communications. One objective of CDR circuitry design is to recover the data from the serial input bit stream in an error-free manner that is efficient in terms of power, die area, and cost.